Apparatus and method for semiconductor device repair with reduced number of programmable elements

ABSTRACT

An apparatus and method using a reduced number of nonvolatile programming elements for enabling redundant memory blocks in a semiconductor memory is disclosed. A redundancy selection module may be configured using N fuses to configure and select 2 N −1 repair modules. Programming fuses effectively separates the repair modules into two sets, those with an even address and those with an odd address. Each repair module contains fuses programmed with a selected address, such that the repair module may respond when an address input matches the selected address. However, the least significant bit is left out of the programming. As a result, repair modules in the even set respond to even addresses matching the selected address and repair modules in the odd set respond to odd addresses matching the selected address. Similar arrangements may be used to reduce the number of enable fuses and disable fuses required for each repair module.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is related to a concurrently filed applicationbearing the Ser. No. 10/862,284.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to semiconductor memory circuits andparticularly to circuits and methods for repairing semiconductor memorycircuits having redundant memory cells.

2. Description of Related Art

Semiconductor memories generally include a multitude of memory cellsarranged in an array of rows and columns. Each memory cell is structuredfor storing digital information in the form of a “1” or a “0” bit. Manysemiconductor memories include extra, i.e., redundant, memory cells thatmay be substituted for failing memory cells. Semiconductor memories aretypically tested after they are fabricated to determine if they containany failing memory cells (i.e., cells to which bits cannot be dependablywritten or from which bits cannot be dependably read). Generally, when asemiconductor memory is found to contain failing memory cells, anattempt is made to repair the memory by replacing the failing memorycells with redundant memory cells provided in redundant rows orredundant columns in the semiconductor memory array.

Conventionally, when a redundant row is used to repair a semiconductormemory containing a failing memory cell, the failing cell's row addressis permanently stored (typically in pre-decoded form) by programmingnonvolatile elements (e.g., fuses, antifuses, Electrically ProgrammableRead-Only memory (EPROM), and FLASH memory cells) on the semiconductormemory. Then, during normal operation of the semiconductor memory, ifthe memory's addressing circuitry receives a memory address including arow address that corresponds to the row address stored on the chip,redundant circuitry in the memory causes access to a redundant rowinstead of the row identified by the received memory address. Sinceevery memory cell in the failing cell's row has the same row address,the redundant row replaces every cell in the failing cell's row, bothoperative and failing, with the redundant memory cells in the redundantrow.

Similarly, when a redundant column is used to repair the semiconductormemory, the failing cell's column address is permanently stored on thechip by programming nonvolatile elements on the chip. Then, duringnormal operation of the semiconductor memory, if the memory's addressingcircuitry receives a memory address including a column address thatcorresponds to the column address stored on the chip, redundantcircuitry in the memory causes a redundant memory cell in the redundantcolumn to be accessed instead of the memory cell identified by thereceived memory address. Since every memory cell in the failing cell'scolumn has the same column address, every cell in the failing cell'scolumn, both operative and failing, is replaced by a redundant memorycell in the redundant column. This process for repairing a semiconductormemory using redundant rows and columns is well known in the art.

A typical semiconductor memory may have many redundant rows and manyredundant columns, each redundant block (whether for a row or column)including its own nonvolatile programming elements for enabling andprogramming the address to which it will respond. As feature sizes onsemiconductor devices continue to shrink, the density of memory cells ona semiconductor die continues to increase, allowing more memory cells ona semiconductor die, which in turn require more redundant rows andcolumns to repair the increased number of memory cells. Because of anincreased number of redundant rows and columns, an increased number ofnonvolatile elements are required to select each redundant row and eachredundant column. Unfortunately, sizes for nonvolatile programmingelements have not reduced proportionately to size reduction for memorycells. As a result, the nonvolatile programming elements take up alarger portion of the available semiconductor die area. In some designs,the nonvolatile programming elements may take up as much as five to tenpercent of the overall semiconductor die area.

It would be advantageous to provide an apparatus and method using areduced number of nonvolatile programming elements associated withrepairing a semiconductor device without compromising overall ability toperform repairs, while reducing area requirements for supportingselection of redundant rows and redundant columns on a semiconductormemory device.

BRIEF SUMMARY OF THE INVENTION

One embodiment of the present invention comprises a semiconductor memoryincluding a plurality of redundant memory blocks, a plurality of repairmodules for selecting the plurality of memory blocks, and at least oneredundancy selection module. The redundancy selection modules may beconfigured to generate select signals for selecting each of theredundant rows and redundant columns when needed to replace a normalmemory row or a normal memory column, respectively. Each redundancyselection module may be configured using N nonvolatile selectionelements to configure and select 2^(N)−1 repair modules. The nonvolatileselection elements may be programmed to a boundary number value betweenzero and an upper boundary of 2^(N) to activate the various selectionsignals for each repair module. The boundary number may then be decodedinto individual select signals, which divide the repair modules into twosets. A first set of repair modules has a quantity equal to the boundarynumber and a second set of repair modules has a quantity equal to theupper boundary less the programmed boundary number.

Each repair module contains nonvolatile address elements, which may beprogrammed with a selected address for that repair module, such that therepair module may respond when an address input matches the selectedaddress. However, one address bit is removed from the programming and isdefined as a configurable address bit. This configurable address bitdoes not have a corresponding nonvolatile address element forcomparison. Instead, the configurable address bit may be compared toselect signals generated from decoding the nonvolatile selectionelements. For an example, assume A0 is used as the configurable addressbit. A first set of repair modules have their select signals de-assertedand may therefore respond to an even address (i.e., when A0 isde-asserted). A second set of repair modules have their select signalsasserted and may therefore respond to an odd address (i.e., when A0 isasserted). This arrangement creates a savings of nonvolatile programmingelements over an arrangement where a nonvolatile address element is usedwithin each repair module for comparison to the configurable addressbit. For example, if N is three, three new nonvolatile selectionelements may be added to create the boundary number; however, seven(i.e., 2^(N)−1) nonvolatile address elements are saved because onenonvolatile address element may be removed from each repair modules,resulting in a net savings of four nonvolatile programming elements.

Each repair module may also contain a nonvolatile enable element forenabling that repair module if it is to be programmed with a selectedaddress, such that the repair module may select a redundant memoryblock. However, another embodiment of the present invention comprisesadding an enable boundary number programming arrangement similar to thatfor the configurable address bit. This may allow removal of the enableelement from each repair module, creating a net savings of fouradditional nonvolatile programming elements in the example defined abovewith seven repair modules.

Another embodiment of the present invention includes a plurality ofsemiconductor memories incorporating the reduced fuse architecturedescribed herein fabricated on a semiconductor wafer.

Another embodiment, in accordance with the present invention, is anelectronic system comprising an input device, an output device, aprocessor, and a memory device. The memory device comprises at least onesemiconductor memory incorporating the reduced fuse architecturedescribed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which illustrate what is currently considered to be thebest mode for carrying out the invention:

FIG. 1 is a block diagram of an exemplary memory bank in a semiconductormemory showing redundancy selection modules for selecting redundantmemory blocks rather than normal memory cells;

FIG. 2 is a block diagram of an exemplary redundancy selection moduleusing nonvolatile selection element encoding;

FIG. 3 is a block diagram of an exemplary repair module with nonvolatileaddress elements, a nonvolatile enable element, and optional nonvolatiledisable element;

FIG. 4 is a block diagram of another exemplary redundancy selectionmodule using nonvolatile enable element encoding;

FIG. 5 is a block diagram of an exemplary repair module without anonvolatile enable element and without a nonvolatile disable element;

FIG. 6 is a block diagram of another exemplary redundancy selectionmodule using nonvolatile disable element encoding;

FIG. 7 is a block diagram of a repair apparatus according to anotherexemplary embodiment of the invention;

FIG. 8 is a semiconductor wafer containing a plurality of semiconductormemories containing redundancy selection modules; and

FIG. 9 is a computing system diagram showing a plurality ofsemiconductor memories containing redundancy selection modules.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, numerous specific details are set forth,such as specific word or byte lengths, etc., to provide a thoroughunderstanding of the present invention. However, it will be readilyapparent to those skilled in the art that the present invention may bepracticed without such specific, but exemplary, details. In otherinstances, circuits have been shown in block diagram form in order notto obscure the present invention in unnecessary detail. Additionally,block definitions and partitioning of logic between various blocks isexemplary of a specific implementation. It will be obvious to one ofordinary skill in the art that the present invention may be practiced bynumerous other partitioning solutions. For the most part, detailsconcerning timing considerations and the like have been omitted inasmuchas such details are not necessary to obtain a complete understanding ofthe present invention and are within the ability of persons of ordinaryskill in the relevant art.

The term “bus” is used to refer to a plurality of signals or conductors,which may be used to transfer one or more various types of information,such as data, addresses, control, or status. Additionally, a bus orcollection of signals may be referred to in the singular as a signal.The terms “assert” and “negate” are respectively used when referring tothe rendering of a signal, status bit, or similar apparatus into itslogically true or logically false state. If the logically true state isa logic level one, the logically false state will be a logic level zero.Conversely, if the logically true state is a logic level zero, thelogically false state will be a logic level one.

Different types of nonvolatile programming elements may be used toimplement the present invention, such as fuses, anti-fuses, laser fuses,Flash memory cells, EPROM cells, mask options and programmable registerbits. These nonvolatile programming elements may be used for variousfunctions within the design. For ease of description and clarity, thenonvolatile programming elements may be referred to by various namessuch as: nonvolatile selection element 212, nonvolatile address element312, nonvolatile enable element 332, and nonvolatile disable element.

Additionally, unless specified otherwise, the nonvolatile programmingelements are assumed to produce a logic “1” as an asserted level whenprogrammed and a logic “0” as a de-asserted level when leftun-programmed.

FIG. 1 is a block diagram of an exemplary memory bank 110 in asemiconductor memory 100 (not shown) in accordance with an embodiment ofthe present invention. A row decode module 120 accepts address inputs150 for decoding into select signals for each row within a normal memorycell array 140. Similarly, a column decode module 130 accepts an addressinput 150 for decoding into select signals for each column within thenormal memory cell array 140. At least one row redundancy selectionmodule 200′ accepts address inputs 150 for decoding and comparing toselected address values such that select signals may be generated foreach redundant row within the redundant memory cell array 145.Similarly, at least one column redundancy selection module 200 acceptsaddress inputs 150 for decoding and comparing to selected address valuessuch that select signals may be generated for each redundant columnwithin the redundant memory cell array 145. Redundant rows and redundantcolumns are also referred to herein generically as redundant memoryblocks 145.

The block diagram shown in FIG. 1 is illustrative of a single memorybank 110. Many modern semiconductor memories are physically organizedessentially as a plurality of memory banks 110 organized as a square orrectangle of memory bits, such that multiple bits are addressed for eachmemory address comprised of a combined row and column address. Thenumber of bits addressed with each memory address may vary, withexemplary amounts being 4, 8, and 16 bits per memory address. As anexample memory architecture, a 512 Mbit DRAM may be separated into fourbanks, each bank containing 128 Mbits. Each bank may typically beconfigured as 8K rows. Each bank may typically comprise 16K columns,which may be organized as 4K columns of four bits, 2K columns of eightbits, or 1K columns of 16 bits. Typical memory addressing is well knownto those skilled in the art, therefore, it is not described in detailherein. Additionally, the arrays of normal memory cells and redundantmemory blocks 145 may be segmented into smaller portions to aid inaddress decoding.

FIG. 2 is an exemplary embodiment of a redundancy selection module 200used to select a set of redundant memory blocks 145 (FIG. 1). Redundancyselection modules for rows and column are typically similar. Therefore,the description of redundancy selection modules 200 applies to bothredundant rows and redundant columns unless specified differentlyherein. Each redundancy selection module 200 comprises a boundaryprogramming module 210, a boundary selection module 220, and a pluralityof repair modules 300. The boundary programming module 210 comprises aset of nonvolatile selection elements 212 for creating an encodedboundary number signal 215. The boundary selection module 220 decodesthe boundary number signal 215 into separate select signals 230 for eachindividual repair module 300. The repair modules 300 are connected to anaddress input 150 bus and the separate select signals 230 generated bythe boundary selection module 220. The address input 150 bus mayrepresent all or portions of a row address or a column address dependingon whether the redundant memory block that may be selected is aredundant row or a redundant column respectively. Each repair module 300includes a match signal output 360, which may be used to select theredundant memory block in place of the normal memory block containingthe faulty memory cell.

Exemplary embodiments of repair modules (300 and 300′) are shownrespectively in FIGS. 3 and 5. In the exemplary embodiment shown in FIG.3, each repair module 300 comprises a set of nonvolatile addresselements 312, an address comparator 320, a select signal comparator 340,a combination element 350, an optional nonvolatile disable element 334that generates an active low disable signal 336, and a nonvolatileenable element 332 that generates an enable signal 330. The selectsignal comparator 340 compares a select signal 230 input to the value onone of the address bits identified as a configurable address bit 152. Asan example of one embodiment, FIGS. 3 and 5 show A0 as the configurableaddress bit 152. For all address inputs 150 to the repair module 300other than the configurable address bit 152, individual address bitcomparators 322, within the address comparator 320, compare the addressinput 150 bus to a selected address 315 programmed into the nonvolatileaddress elements 312 FZA1 through FZAn. In FIG. 5, the optionalnonvolatile disable element 334 is not shown and the enable signal 330is an input to the repair module 300′, the function of which isexplained more fully below.

In the embodiment shown in FIG. 3, the optional nonvolatile disableelement 334, if present, is active low such that programming thenonvolatile disable element 334 generates a logic zero on the disablesignal 336, which disables a match signal 360 from being asserted. Whenthe nonvolatile disable element 334 is left unprogrammed, a logic highon the disable signal 336 allows a match signal 360 to be asserted. Anonvolatile enable element 332 within the repair module 300 drives theenable signal 330. If the nonvolatile enable element 332 is leftun-programmed, the repair module 300 may be disabled such that a matchsignal 360 may not be asserted. If the nonvolatile enable element 332 isprogrammed, the combination element 350 may assert the match signal 360when combined with a matching result from the address comparator 320 anda matching result from the select signal comparator 340. When asserted,the match signal 360 may select the redundant memory block foroperation. In some memory architectures, the match signal 360 may beused to select the redundant memory block and deselect the defectivememory block. In other architectures, the defective memory block may beindependently disabled. Note that the combination element 350 is shownas a multi-input AND gate and the compare functions as EXCLUSIVE-ORgates to show logical function only, not physical implementation. Thecombination and compare functions may be implemented in many bit widths,as well as physical configurations, such as, for example, cascaded logicgates, pre-charge and evaluate type implementations, and pre-chargedomino type implementations.

Within the redundancy selection module 200, as shown in FIG. 2, thenonvolatile selection elements 212 (FZS0, FZS1, and FZS2) may beprogrammed to represent a boundary number between zero and an upperboundary number 228 of 2^(NSE)−1, where NSE is the number of nonvolatileselection elements 212. With three nonvolatile selection elements 212,as shown in FIG. 2, the boundary number may be programmed to a value ofzero through seven. Similarly, for two nonvolatile selection elements212 (not shown), the boundary number may be programmed to a value ofzero through three and for four nonvolatile selection elements 212 (notshown), the boundary number may be programmed to a value of zero throughfifteen. The number of nonvolatile programming elements may be expandedfor larger groupings of repair modules 300, such as, for example, fournonvolatile selection elements 212 controlling 15 repair modules 300, orfive nonvolatile selection elements 212 controlling 31 repair modules300. In the exemplary embodiment shown in FIG. 2, the boundary number isencoded as a binary number; however, other encodings, such as, forexample, Johnson or pseudo-random encodings, are possible and within thescope of the present invention.

The boundary number signal 215 connects to a boundary selection module220 comprising decode logic for converting the encoded boundary numbersignal 215 into individual select signals 230 for each of the repairmodules 300. In the embodiment shown in FIG. 2, the decoding is atypical priority decoder. Select signals connecting the boundaryselection module 220 to a plurality of repair modules 300 may be thoughtof as being numbered from zero to one less than the upper boundarynumber 228. For example, in the embodiment shown in FIG. 2, the selectsignals 230 may be thought of as numbered from sel0 to sel6. Once aboundary number value 225 is programmed, all select signals 230 equal toor greater than the boundary number value 225 are asserted and allselect signals 230 less than the boundary number value 225 arede-asserted. For example, for a boundary number of “000,” all selectsignals 230 are asserted while for a boundary number of “111,” allselect signals 230 are de-asserted. As shown in FIG. 2, for a boundarynumber of “111,” select signals 230 sel3 through sel6 are asserted whileselect signals 230 sel0 through sel2 are de-asserted. In other words,the encoded boundary number signal 215, in combination with the boundaryselection module 220, in effect, creates two logical sets of selectsignals 230 connected to two logical sets of repair modules 300. Asshown in FIG. 2 for a boundary number of “011,” the first set ofde-asserted select signals 230, comprising all select signals 230 lessthan the boundary number (sel0 through sel2), connect to a first set ofrepair modules 232. Similarly, a second set of asserted select signals230, comprising all select signals 230 equal to or greater than theboundary number (sel3 through sel6), connect to a second set of repairmodules 234. This partitioning into sets is a logical partitioningsimply for the convenience of describing the present invention.Obviously, the partitioning between the first set and the second setchanges for different boundary number values 225.

To configure each redundancy selection module 200 for operation, thenonvolatile address elements 312 (FZA1–FZAN) in each repair module 300may be programmed to a unique selected address 315 representing theaddress of a defective normal memory block. For each repair module 300intended to select a redundant memory block as a replacement for adefective memory block, the nonvolatile enable element 332 for thatrepair module 300 may also be programmed. For the entire redundancyselection module 200, the nonvolatile selection elements 212 areprogrammed to the desired boundary number value 225.

The programmed boundary number value 225 defines which repair modules300 will respond to an asserted configurable address bit 152 and whichrepair modules 300 will respond to a de-asserted configurable addressbit 152. As an example of one embodiment, FIG. 3 shows A0 as theconfigurable address bit 152. In this embodiment, the boundary numbercan be thought of as defining the first set of repair modules 232 (notshown) as those which will respond to an even addresses (i.e., A0 isde-asserted) and the second set of repair modules 234 (not shown) asthose which will respond to an odd address (i.e., A0 is asserted). Adifferent address bit may be selected as the configurable address bit152 in practicing the present invention. For example, if the mostsignificant address bit is selected, the boundary number can be thoughtof as defining the first set of repair modules 232 as those in the lowerhalf of a memory block and the second set of repair modules 234 as thosein the upper half of a memory block.

Returning to FIG. 3 where A0 is shown as the configurable address bit152, in the prior art each repair module 300 contained a nonvolatileaddress element 312 (not shown) for matching to A0 using an address bitcomparator 322 similar to the address bit comparators 322 used for theother address bits. However, the present invention takes advantage ofthe fact that every address input 150 is either even or odd. By removingA0 from the address comparison, a nonvolatile address element 312 issaved in each the repair modules 300. For the embodiment shown in FIG.3, seven nonvolatile programming elements are saved. The nonvolatileselection elements 212 in the boundary programming module 210 are usedinstead for selecting which repair modules 300 respond to odd addressesand which repair modules 300 respond to even addresses. As a result,seven nonvolatile address elements 312 are saved and three newnonvolatile selection elements 212 are added, resulting in a savings offour nonvolatile programming elements for each redundancy selectionmodule 200. As an example of redundant column selection, for a columnaddress with eight address bits, the prior art used nine nonvolatileprogramming elements for each repair module 300 (eight for address andone for enable) for a total of 63 nonvolatile programming elements. Thepresent invention, in the embodiment shown in FIG. 2, uses eightnonvolatile programming elements for each of the seven repair modules300 (seven for A1–A8 and one for enable) plus three new nonvolatileprogramming elements for the boundary number for a total of 59nonvolatile programming elements. A total savings of 6.3% is achievedfor each redundancy selection module 200 used on the semiconductormemory 100 without sacrificing any reparability.

As an operational example, if after testing the semiconductor memory100, five column addresses are determined to produce incorrect results,the five defective columns may be replaced by five redundant columns.Therefore, five of the seven repair modules 300 may be enabled byprogramming the nonvolatile enable element 332 in those five repairmodules 300. For the FIG. 2 embodiment, repair modules 300 zero throughfour may be enabled while repair modules 300 five and six remaindisabled. Each of the five defective columns has a unique addresscomprised of nine bits (i.e., A0–A8). After examining the five uniqueaddresses, it is determined that three addresses are even and twoaddresses are odd. Using this determination, the nonvolatile selectionelements 212 in the boundary programming module 210 may be programmed tothe number of required even addresses. In the case of three evenaddresses, the boundary number may be programmed to the value of three.A boundary number of three may generate a de-asserted select signal forsel0, sel1, and sel2 and an asserted select signal for sel3, sel4, sel5,and sel6. The state of sel5 and sel6 are unimportant in this examplebecause repair modules 300 five and six are not enabled. Address bitsA1–8 of the unique addresses for each defective column with an evenaddress are programmed as the selected address 315 for each of therepair modules 300 zero, one, and two. Address bits A1–8 of the uniqueaddresses for each defective column with and odd address are programmedas the selected address 315 for each of the repair modules 300 three andfour.

After completing the programming, each repair module 300 may generate amatch signal 360 only for its unique nine-bit selected address 315. Forexample, assume repair module two 300 is programmed to respond to anaddress input 150 of 32 decimal (0 0001 0000 binary). The addresscomparison on A1–A8 may generate a match for address inputs 150 valuesof 32 and 33 since the only difference between 32 and 33 is bit A0.However, since sel2 is de-asserted, the repair module 300 may onlygenerate a final match signal 360 when A0 is de-asserted. Therefore, anaddress input 150 of 32 may generate a match signal 360 while an addressinput 150 of 33 may not generate a match signal 360.

Additional nonvolatile programming element savings are possible by usinga similar boundary encoding mechanism for the enable signals 330. FIG. 4shows an exemplary embodiment of a redundancy selection module 200′using the boundary selection for the configurable address bit 152 asdescribed above as well as a boundary selection for the enable signals330. The boundary programming module 210 and boundary selection module220 for the configurable address bit 152 are shown without the internaldetails. An enable boundary programming module 260 and an enableboundary selection module 270 are shown generating the enable signals330. In this exemplary embodiment, a slightly modified repair module300′ may be used. As shown in FIG. 5, the nonvolatile enable element 332within the repair module 300′ may be removed leaving the enable signal330 as an input to the repair module 300′. Referring back to FIG. 4, thefunction and configuring of the enable boundary programming module 260and enable boundary selection module 270 are similar to those describedabove for the configurable address bit 152. Therefore, only a briefdescription of configuring the boundary for the enable signals 330 isrequired. As an example, an enable boundary number 265 of “101,” may beprogrammed into the nonvolatile enable elements 332′ such that theenable signals 330 for a set of enabled repair modules 282 (i.e., zerothrough four) may be asserted and the enable signals 330 for a set ofdisabled repair modules 284 (i.e., five and six) may be de-asserted. Aswith the configurable encoded boundary number signal 215, the logicalpartitioning into a set of enabled repair modules 282 and a set ofdisabled repair modules 284 is for convenience of describing the presentinvention and the partitioning between the enabled set and the disabledset changes for different enable boundary number signals 265. Inaddition, the number of nonvolatile elements may be expanded for largergroupings of repair modules 300′, such as, for example, four nonvolatileenable elements 332′ controlling 15 repair modules 300′, or fivenonvolatile enable elements 332, controlling 31 repair modules 300′.

Of course, if desired, the reduced fuse programming using a boundaryselection for the enable signals 330 may also be used separately fromthe reduced fuse programming using a boundary selection for aconfigurable address bit 152.

In some other embodiments, each repair module 300 may have thenonvolatile disable element 334. The disable function may be needed in acase where a redundant memory block contains a faulty memory bit andshould therefore be disabled from being a candidate for use as aredundant memory block. In addition, the disable function may be neededif a fault or error occurs in the attempt to program a repair module300. For any given repair module 300, the disable function may overrideany other nonvolatile element programming within that repair module 300.

The disable function may also be encoded for a group of repair modules300. FIG. 6 shows an exemplary embodiment using the boundary selectionfor the configurable address bit 152 as described above, as well as adisable selection for the disable signals 336. The boundary programmingmodule 210 and boundary selection module 220 for the configurableaddress bit 152 are shown without the internal details. A disableprogramming module 280 and a disable decoder 290 are shown generatingthe disable signals 336. In this exemplary embodiment, the repair module300 of FIG. 3 may be used without the optional nonvolatile disableelement 334, such that the disable signal 336 is an input to the repairmodule 300.

As shown in FIG. 6, the disable function for one of a group of repairmodules 300 may be binary encoded using a simple “one-hot” decoding toselect one of the repair modules 300 to be disabled. This encodingmechanism results in a savings of seven disable fuses and an addition ofthree encoded disable fuses for a net savings of four nonvolatileprogramming elements. The nonvolatile disable elements 334′ are activelow such that programming generates a logic zero. As a result, thedisable decoder 290 decodes active low signals. Similarly, the disablesignals 336 are active low. Accordingly, the disable decoder 290generates a logic low for the decoded disable signal 336 and a logic onefor all other disable signals.

For example, in a redundancy selection module 200″ configured with sevenrepair modules 300, the disable programming module 280 uses threenonvolatile disable elements 334′ to generate a disable number 285. Ifrepair module three 300 or redundant memory block three 145 contains adefect, “100” may be programmed into the three nonvolatile disableelements 334′ to disable repair module three 300 while leaving all otherrepair modules 300 available. In other words, FZD0 and FZD1 areprogrammed, and FZD2 remains un-programmed.

Typically, not more than one repair module 300 in a group of seven wouldrequire disabling. However, a second group of three may be added todisable a second repair module 300 and still result in a net savings ofone nonvolatile disable element (i.e., 2*3 encoded elements added, 7individual elements removed). Obviously, the binary encoding of disableelements can be expanded for larger groupings of repair modules 300,such as, for example, 15 or 31 repair modules 300 within a redundancyselection module 200.

Embodiments of the present invention have been described in relation tosemiconductor memories including redundant memory cells. However, thepresent invention is applicable as a repair apparatus in other systemsand devices where a reduced number of programmable elements are desired.FIG. 7 illustrates a repair apparatus 400 according to another exemplaryembodiment of the invention. The repair apparatus includes normalelements 440, redundant elements 445, a normal selection module 420, aredundant selection module 200, and an address input bus 450. In theFIG. 7 embodiment, redundant elements may include memory rows, memorycolumns, memory arrays, register files, execution units, and processors.

As examples, in fault tolerant systems containing redundant processors,the present invention may be used to disable certain processors fromoperation or participation in a voting process. Alternatively, thepresent invention may be used to select redundant processors in place ofnormal processors. In another example, processors may contain normalexecution units and redundant execution units, such as arithmetic logicunits and the like. The present invention may select redundant executionunits to replace faulty execution units. Similarly, a processor maycontain redundant register files to replace faulty register files.Moreover, the term faulty may be defined as producing a desired resulttoo slowly, rather than incorrectly. As a result, it may be desirable toselect redundant elements, such as, for example, execution units orredundant register files, which may operate faster than normal executionunits or normal register files may operate.

As shown in FIG. 8, a semiconductor wafer 490, in accordance with thepresent invention, includes a plurality of semiconductor memories 100incorporating the reduced fuse architecture described herein. Of course,it should be understood that the semiconductor memories 100 may befabricated on substrates other than a silicon wafer, such as, forexample, a Silicon On Insulator (SOI) substrate, a Silicon On Glass(SOG) substrate, and a Silicon On Sapphire (SOS) substrate.

As shown in FIG. 9, an electronic system 500, in accordance with thepresent invention, comprises an input device 510, an output device 520,a processor 530, and a memory device 540. The memory device 540comprises at least one semiconductor memory 100 incorporating thereduced fuse architecture described herein in a DRAM device. It shouldbe understood that the semiconductor memory 100 might comprise a widevariety of devices other than a DRAM, including, for example, Static RAM(SRAM) devices and Flash memory devices.

Although this invention has been described with reference to particularembodiments, the invention is not limited to these describedembodiments. Rather, the invention is limited only by the appendedclaims, which include within their scope all equivalent devices ormethods that operate according to the principles of the invention asdescribed.

1. A repair apparatus for repairing a semiconductor device, comprising:a plurality of redundant elements; at least one configurable addressbit; a plurality of repair modules comprising; a first set of repairmodules, wherein each repair module in the first set of repair modulesmay be configured to select one of the plurality of redundant elementswhen the at least one configurable address bit is de-asserted; and asecond set of repair modules, wherein each repair module in the secondset of repair modules may be configured to select one of the pluralityof redundant elements when the at least one configurable address bit isasserted; and at least one redundancy selection module configured forprogramming a boundary number, wherein the boundary number defines whichof the plurality of repair modules are in the first set of repairmodules, and which of the plurality of repair modules are in the secondset of repair modules.
 2. The repair apparatus of claim 1, wherein theat least one redundancy selection module comprises: a plurality of Nnonvolatile selection elements configured for programming the boundarynumber; and a boundary selection module, wherein the boundary number maybe decoded to select a quantity of repair modules equal to the boundarynumber as the first set of repair modules, and select a quantity ofrepair modules equal to 2^(N)−1 less the boundary number as the secondset of repair modules.
 3. The repair apparatus of claim 2, wherein theplurality of N nonvolatile selection elements are selected from thegroup consisting of fuses, anti-fuses, laser fuses, Flash memory cells,EPROM cells, mask options, and programmable register bits.
 4. The repairapparatus of claim 1, wherein each of the plurality of repair modulescomprises: a plurality of nonvolatile address elements configured forprogramming a selected address; a select signal configured to indicate arepair module is in the first set of repair modules when the selectsignal is de-asserted or in the second set of repair modules when theselect signal is asserted; and an enable signal, wherein the repairmodule may select one of the plurality of redundant elements when theenable signal is asserted, an address input corresponds with theselected address, and the at least one configurable address bitcorresponds with the select signal.
 5. The repair apparatus of claim 4,wherein the plurality of nonvolatile address elements are selected fromthe group consisting of fuses, anti-fuses, laser fuses, Flash memorycells, EPROM cells, mask options, and programmable register bits.
 6. Therepair apparatus of claim 4, wherein each of the plurality of repairmodules further comprise a nonvolatile enable element configured forprogramming the enable signal.
 7. The repair apparatus of claim 6,wherein the plurality of nonvolatile address elements and thenonvolatile enable element are selected from the group consisting offuses, anti-fuses, laser fuses, Flash memory cells, EPROM cells, maskoptions, and programmable register bits.
 8. The repair apparatus ofclaim 1, further comprising: a plurality of nonvolatile enable elementsconfigured for programming an enable boundary number, wherein the enableboundary number defines a set of enabled repair modules that may beenabled for selecting one of the plurality of redundant elements and aset of disabled repair modules that are disabled from selecting one ofthe plurality of redundant elements.
 9. The repair apparatus of claim 8,wherein each of the plurality of repair modules comprises; a pluralityof nonvolatile address elements configured for programming a selectedaddress; and a select signal configured to indicate a repair module isin the first set of repair modules when the select signal is de-assertedor in the second set of repair modules when the select signal isasserted, wherein each of the plurality of repair modules may select oneof the plurality of redundant elements when the repair module isenabled, an address input corresponds with the selected address, and theat least one configurable address bit corresponds with the selectsignal.
 10. The repair apparatus of claim 9, wherein the plurality ofnonvolatile enable element elements and the plurality of nonvolatileaddress elements are selected from the group consisting of fuses,anti-fuses, laser fuses, Flash memory cells, EPROM cells, mask options,and programmable register bits.
 11. The repair apparatus of claim 1,wherein the plurality of redundant elements are selected from the groupconsisting of memory rows, memory columns, memory arrays, registerfiles, execution units, and processors.
 12. A semiconductor memory,including a plurality of redundant memory blocks comprising: at leastone configurable address bit; a plurality of repair modules comprising;a first set of repair modules, wherein each repair module in the firstset of repair modules may be configured to select one of the pluralityof redundant memory blocks when the at least one configurable addressbit is de-asserted; and a second set of repair modules, wherein eachrepair module in the second set of repair modules may be configured toselect one of the plurality of redundant memory blocks when the at leastone configurable address bit is asserted; and at least one redundancyselection module configured for programming a boundary number, whereinthe boundary number defines which of the plurality of repair modules arein the first set of repair modules and which of the plurality of repairmodules are in the second set of repair modules.
 13. The semiconductormemory of claim 12, wherein the at least one redundancy selection modulefurther comprises: a plurality of N nonvolatile selection elementsconfigured for programming the boundary number; and a boundary selectionmodule, wherein the boundary number may be decoded to select a quantityof repair modules equal to the boundary number as the first set ofrepair modules, and select a quantity of repair modules equal to 2^(N)−1less the boundary number as the second set of repair modules.
 14. Thesemiconductor memory of claim 13, wherein the plurality of N nonvolatileselection elements are selected from the group consisting of fuses,anti-fuses, laser fuses, Flash memory cells, EPROM cells, mask options,and programmable register bits.
 15. The semiconductor memory of claim12, wherein each of the plurality of repair modules comprises: aplurality of nonvolatile address elements configured for programming aselected address; a select signal configured to indicate a repair moduleis in the first set of repair modules when the select signal isde-asserted or in the second set of repair modules when the selectsignal is asserted; and an enable signal, wherein the repair module mayselect one of the plurality of redundant memory blocks when the enablesignal is asserted, an address input corresponds with the selectedaddress, and the at least one configurable address bit corresponds withthe select signal.
 16. The semiconductor memory of claim 15, wherein theplurality of nonvolatile address elements is selected from the groupconsisting of fuses, anti-fuses, laser fuses, Flash memory cells, EPROMcells, mask options, and programmable register bits.
 17. Thesemiconductor memory of claim 15, wherein each of the plurality ofrepair modules further comprise a nonvolatile enable element configuredfor programming the enable signal.
 18. The semiconductor memory of claim17, wherein the plurality of nonvolatile address elements and thenonvolatile enable element are selected from the group consisting offuses, anti-fuses, laser fuses, Flash memory cells, EPROM cells, maskoptions, and programmable register bits.
 19. The semiconductor memory ofclaim 12, further comprising: a plurality of nonvolatile enable elementsconfigured for programming an enable boundary number, wherein the enableboundary number defines a set of enabled repair modules that may beenabled for selecting one of the plurality of redundant memory blocksand a set of disabled repair modules that are disabled from selectingone of the plurality of redundant memory blocks.
 20. The semiconductormemory of claim 19, wherein each of the plurality of repair modulescomprises: a plurality of nonvolatile address elements configured forprogramming a selected address; and a select signal configured toindicate a repair module is in the first set of repair modules when theselect signal is de-asserted or in the second set of repair modules whenthe select signal is asserted, wherein each of the plurality of repairmodules may select one of the plurality of redundant memory blocks whenthe repair module is enabled, an address input corresponds with theselected address, and the at least one configurable address bitcorresponds with the select signal.
 21. The semiconductor memory ofclaim 20, wherein the plurality of nonvolatile enable elements and theplurality of nonvolatile address elements are selected from the groupconsisting of fuses, anti-fuses, laser fuses, Flash memory cells, EPROMcells, mask options, and programmable register bits.
 22. A method ofconfiguring a semiconductor device bearing a plurality of redundantelements thereon, comprising: defining at least one configurable addressbit; configuring a plurality of repair modules corresponding to theplurality of redundant elements with a selected address such that eachof the plurality of repair module may be enabled to respond when anaddress input matches the selected address for a repair module; andconfiguring the plurality of repair modules into a first set of repairmodules that may respond to a de-asserted level on the at least oneconfigurable address bit and a second set of repair modules that mayrespond to an asserted level on the at least one configurable addressbit.
 23. The method of claim 22, wherein configuring each of theplurality of repair module with a selected address comprises:programming a plurality of nonvolatile address element to a valuerepresenting the selected address.
 24. The method of claim 22, whereinconfiguring the plurality of repair modules further comprises:programming a plurality of N nonvolatile selection elements to representa boundary number wherein, the first set of repair modules comprises aquantity of repair modules equal to the boundary number; and the secondset of repair modules comprises a quantity of repair modules equal to2^(N)−1 less the boundary number.
 25. The method of claim 22, furthercomprising programming a plurality of NE nonvolatile enable elements torepresent an enable boundary number, wherein the enable boundary numberdefines a set of enabled repair modules equal to the enable boundarynumber and a set of disabled repair modules equal to 2^(NE)−1 less theenable boundary number.
 26. The method of claim 22, further comprisingprogramming a nonvolatile enable element corresponding to each of theplurality of repair modules, wherein each repair module may be enabledwhen the nonvolatile enable element corresponding to that repair moduleis programmed.
 27. The method of claim 26, further comprisingprogramming a nonvolatile disable element corresponding to each of therepair modules, wherein each repair module may be disabled when thenonvolatile enable element corresponding to that repair module isprogrammed.
 28. The method of claim 26, further comprising programming aplurality of nonvolatile disable elements to represent a disable number,wherein the disable number may be decoded to disable one of theplurality of repair modules.
 29. A method of selecting a plurality ofredundant memory blocks on a semiconductor memory, comprising: enablingeach of a plurality of repair modules corresponding to one of theplurality of redundant memory blocks in which an address inputcorresponds to a selected address configured for that repair module;selecting a redundant memory block of the plurality of redundant memoryblocks if the corresponding repair module is enabled and configured torespond to a de-asserted level on at least one configurable address bit;and selecting another redundant memory block of the plurality of memoryblocks if the other corresponding repair module is enabled andconfigured to respond to an asserted level on the at least oneconfigurable address bit.
 30. The method of claim 29, further comprisingdisabling the selecting a redundant memory block when a nonvolatiledisable element in the repair module corresponding to that redundantmemory block is programmed.
 31. The method of claim 29, furthercomprising disabling the selecting another redundant memory block when anonvolatile disable element in the repair module corresponding to thatredundant memory block is programmed.
 32. A semiconductor wafer,comprising: at least one semiconductor device including a repairapparatus, comprising: a plurality of redundant elements; at least oneconfigurable address bit; a plurality of repair modules comprising; afirst set of repair modules, wherein each repair module in the first setof repair modules may be configured to select one of the plurality ofredundant elements when the at least one configurable address bit isde-asserted; and a second set of repair modules, wherein each repairmodule in the second set of repair modules may be configured to selectone of the plurality of redundant elements when the at least oneconfigurable address bit is asserted; and at least one redundancyselection module configured for programming a boundary number, whereinthe boundary number defines which of the plurality of repair modules arein the first set of repair modules, and which of the plurality of repairmodules are in the second set of repair modules.
 33. An electronicsystem, comprising: at least one input device; at least one outputdevice; a processor; and a memory device comprising, at least onesemiconductor memory including a repair apparatus, comprising: aplurality of redundant elements; at least one configurable address bit;a plurality of repair modules comprising; a first set of repair modules,wherein each repair module in the first set of repair modules may beconfigured to select one of the plurality of redundant elements when theat least one configurable address bit is de-asserted; and a second setof repair modules, wherein each repair module in the second set ofrepair modules may be configured to select one of the plurality ofredundant elements when the at least one configurable address bit isasserted; and at least one redundancy selection module configured forprogramming a boundary number, wherein the boundary number defines whichof the plurality of repair modules are in the first set of repairmodules, and which of the plurality of repair modules are in the secondset of repair modules.